> Thin Wafer Applications & Related Technologies
>>By 2017, the ratio of thin wafers vs. total number of wafers will be 74% in 12’’ eq.
Wednesday, November 14, 2012, 8:00 AM PST
Powered by Yole Développement
Hosted by I-micronews.com
Sponsored by EV Group
Dr. Eric Mounier, Yole Développement
Markus Wimplinger, Corporate Technology Development and IP Director
Mike McLaughlin, Business Development, Yole Inc .
Consumer electronics is a big driver for smaller, higher performing, lower cost device configurations for use in applications such as memory, wireless devices, and others. These new configurations are, in turn, pushing demand for thin (< 100 µm) and even ultra-thin semiconductor wafers (below 40µm) with the following benefits:
- Reduced thickness, equating to thinner packages
- Wafer thinning is the most efficient approach used for heat dissipation in thermal management
- For 3D integration, thin wafers offer higher density for through Si vias
However, as wafer thickness decreases to 100µm and below, manufacturing challenges arise. Ultra-thin wafers are less stable and more vulnerable to stress, and the die could be prone to breaking and warping -- not only during grinding, but also at subsequent processing steps. Thus, special thin wafer handling processes (such as temporary bonding) are necessary, especially when wafers are dual-side processed or have high topographies.
This webcast will present an overview of the thin wafers market, its applications and related processes.
It will cover the following applications:
- CMOS Image Sensors
- Power Devices
- Memory & Logic
- Interposers and Advanced Packaging
Since 1998, Dr Eric Mounier is a co-founder of Yole Développement, a market research company based in France. At Yole Développement, Dr. Eric Mounier is in charge of market analysis for MEMS, equipment & material. He is Chief Editor of Micronews, and MEMS’Trends magazines. Dr. Eric Mounier has a PhD in microelectronics from the INPG in Grenoble.
Markus Wimplinger, is director of EV Group’s (EVG) business unit for technology development and intellectual property. In this role, Markus oversees EV Group’s global process engineering team. Additional responsibilities include the management of R&D partnerships and contracts with third-party organizations such as companies or government-related entities, as well as intellectual property affairs associated with EVG’s process technology development efforts and 3D integration-related projects.
Mike McLaughlin has been working with emerging technologies for over 12 years at IBM and Cisco and was a principal analyst at Gartner. He now leads all of Yole Développement's activities and business development for North America. Mike is a graduate of Stanford University in Palo Alto, CA